Identifying defects in deep-submicron CMOS ICs

Given the oft-cited difficulty of testing modern integrated circuits, the fact that CMOS ICs lend themselves to IDDQ testing is a piece of good fortune. But that valuable advantage is threatened by the rush of semiconductor technology to smaller feature sizes and faster, denser circuits, in line with the Semiconductor Industry Association's (SIA) Roadmap--its forecast for the CMOS IC industry. With safety margins for reliability, test, failure analysis, and design verification shrinking, it would be a shame to give up the IDDQ technique--and luckily, we may not have to. Steps can be taken to maintain its applicability as we rush deeper into the submicron regime. Before discussing them, however, a brief discussion of IDDQ testing seems to be in order. We will first examine why the IDDQ test serves several interests, then describe the challenge posed by 0.35-0.07-μm transistor geometries, and finally propose several solutions. CMOS IC power supply current can be amperes during logic state transitions, but only nanoamperes during the steady state, or quiescent, portion of the clock cycle. This low quiescent power supply current, known as IDDQ, is what gives CMOS its traditional lowpower edge over its technology competitors. But it does more than that. Engineers in design, fabrication, and test have learned to use this low quiescent current as a sensitive test to identify defects, which often prove to be the reason for customer returns, whether as test escapes or reliability failures. In fact, test escape levels below 200 parts per million have recently been attainable only by adding IDDQ testing. The technique has also eliminated the need for burn-in for some mature product lines. More, IDDQ measurements speed failure analysis by providing current-voltage signatures and temporal characteristics.